1. Field of the Invention
This invention relates to a method of driving a plasma display panel, and more particularly to a method of driving a plasma display panel wherein a selective inversion system is used to perform an addressing operation.
2. Description of the Related Art
Recently, a plasma display panel (PDP) feasible to a manufacturing of a large-dimension panel has been highlighted as a flat panel display device. The PDP usually controls a discharge period of each pixel in accordance with a digital video data to thereby display a picture. The PDP typically includes a three-electrode, alternating current (AC) type PDP that has three electrodes and is driven with an AC voltage as shown in FIG. 1.
FIG. 1 shows a structure of each discharge cell arranged in a matrix type in a conventional AC type PDP.
Referring to FIG. 1, the PDP includes an upper plate provided with a sustain electrode pair 12A and 12B, an upper dielectric layer 14 and a protective film 16 that are sequentially formed on an upper substrate 10 of the discharge cell, and a lower plate provided with a data electrode 20, a lower dielectric layer 22, barrier ribs 24 and a fluorescent layer 26 that are sequentially formed on a lower substrate 18 thereof. The upper substrate 10 and the lower substrate 18 are spaced in parallel by the barrier ribs 24. Each of the sustain electrode pair 12A and 12B consists of a transparent electrode having a relatively large width to transmit a visible light and a metal electrode having a relatively small width to compensate for a resistance component of the transparent electrode. Such a sustain electrode pair 12A and 12B consists of a scan electrode 12A and a sustain electrode 12B. The scan electrode 12A mainly applies a scan signal for a panel scanning and a sustain signal for a discharge sustaining, whereas the sustain electrode 12B mainly applies a sustain signal. Electric charges are accumulated in the upper and lower dielectric layers 14 and 22. The protective film 16 prevents a damage of the upper dielectric layer 14 caused by the sputtering to prolong a life of the PDP as well as to improves the emission efficiency of secondary electrons. This protective film 16 is usually made from MgO.
These dielectric layers 14 and 22 and protective film 16 can lower a discharge voltage applied from the exterior thereof. A data electrode 20 crosses the sustain electrode pair 12A and 12B. This data electrode 20 supplies a data signal for selecting cells to be displayed. The barrier ribs 24 are formed in parallel to the data electrode 20 to prevent a ultraviolet ray generated by the discharge from being leaked into adjacent cells. The fluorescent layer 26 is coated on the surfaces of the lower dielectric layer 22 and the barrier ribs 24 to generate any one of red, green and blue visible lights. A discharge space is filled with an inactive gas, such as He, Ne, Ar, Xe and Kr, etc., for a gas discharge, a discharge gas consisting of a combination of said inactive gases or an Excimer gas capable of generating an ultraviolet ray by the discharge.
The discharge cell having the structure as mentioned above is selected by an opposite discharge between the data electrode 20 and the scan electrode 12A to keep the discharge by the surface discharge between the sustain electrode pair 12A and 12B. In the discharge cell, the fluorescent layer 26 is radiated by an ultraviolet ray generated upon sustain discharge to emit a visible light into the exterior of the cell. In this case, the discharge cell controls a discharge sustain period, that is, a sustain discharge frequency of the cell in accordance with a video data to implement a gray scale required for an image display.
FIG. 2 shows an electrode arrangement structure of a three-electrode, AC type PDP having the discharge cells shown in FIG. 1 arranged in a matrix type.
Referring to FIG. 2, a discharge cells 30 is provided at each intersection among scan electrode lines Y1 to Ym, sustain electrode lines Z1 to Zm and data electrode lines X1 to Xn. The scan electrode lines Y1 to Ym apply scan pulses and sustain pulses to scan the discharge cells 30 for each line and keep the discharge at the discharge cells 30. The sustain electrode lines Z1 to Zm commonly applies sustain pulses to keep the discharge at the discharge cells 30 along with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn applies data pulses synchronized with the scan pulses for each line to select the discharge cells 30 in accordance with logical values of the data pulses.
Such a PDP driving method typically includes an address and display separation (ADS) driving method wherein the PDP is driven with being divided into an address period and a display period, that is, a discharge sustain period. In the ADS driving method, as shown in FIG. 3, one frame 1F is divided into 8 sub-fields SF1 to SF8 corresponding to each bit of 8-bit image data. Each sub-field SF1 to SF8 is again divided into a reset period RPD, an address period APD and a sustain period SPD.
The reset period RPD provides an initial condition for permitting the next addressing operation. In other words, the reset period RPD allows wall charges to have a reproducible and constant state just before the address period APD for the purpose of providing each cell with a stable operation having a uniform brightness. The address period APD selects cells to be turned on and cells to be turned off depending upon the data pulses. The sustain period SPD keeps a discharge for the cells having turned on in the address period APD. The reset period RPD and the address period APD of each sub-field SF1 to SF8 are equal, and the sustain period SPD is given with a weighting value of a ratio of 20:21:22: . . . :2n−1 to express a gray scale by a combination of the sustain periods SPD.
In such an ADS driving method, the addressing method is largely classified into a selective write method and a selective erase method.
FIG. 4 is a flow chart representing a driving sequence of one sub-field according to the selective write addressing method.
The selective write addressing method applies above a discharge initiation voltage between the scan electrode and the data electrode so as to selectively turn on the discharge cells in accordance with a data to thereby generate a discharge.
More specifically, at step S10, an entire write discharge is generated at all the cells of the panel with the aid of the reset pulse and thereafter is turned to an off state having the residual wall charges so as to initialize the PDP. At steps S12 to S16, the cells are selected in accordance with a display data such that a write discharge is generated at the cells to be turned on with the aid of the scan pulses and the data pulses and a discharge is not generated at the cells to be turned off. At step S18, a sustain operation is performed during the corresponding interval of the on/off state of the cell determined at said steps S14 and S16 to thereby realize a gray scale. Particularly, the cells having the on state by the write discharge at said step S14 keeps the discharge during the corresponding interval. Subsequently, at step S20, an erasure operation allowing all the cells to have an off state is performed to prepare the next sub-field operation. At the next sub-field, the PDP repeats the operations of said steps S10 to S20.
FIG. 5 is a driving waveform diagram for explaining the PDP driving method employing the above-mentioned selective write addressing method. Herein, X represents a signal waveform applied to the data electrode 20; Y represents a signal waveform applied to the scan electrode 12A; and Z represents a signal waveform applied to the sustain electrode 123, in one sub-field interval.
In FIG. 5, in the reset period RPD, an entire write discharge is generated with the aid of a reset pulse RP and thereafter wall charges are erased, thereby initializing the cells into an off state having the residual wall charges.
More specifically, the reset pulse RP has a positive-going ramp pulse slowly increasing into a peak voltage Vr on a basis of a step voltage Vs and a negative-going ramp pulse slowing decreasing into a ground voltage (0V). By this positive-going ramp pulse, a primary dark discharge is generated between the scan electrode 12A and the sustain electrode 12B and between the scan electrode 12A and the data electrode 20. This dark discharge forms negative wall charges on the scan electrode 12A while forming positive wall charges on the sustain electrode 12B and the data electrode 20. Then, a secondary dark discharge is generated between the two electrodes 12A and 12B with the aid of the negative-going ramp pulse applied to the scan electrode 12A and a bias voltage pulse BP applied to the sustain electrode 12B. Subsequently, since the scan electrode 12A pulls positive ions generated by the secondary dark discharge while the sustain electrode 12B pulls electrons, wall charges formed on the scan electrode 12A and the sustain electrode 12B are reduced in accordance with a decrease of the negative-going ramp voltage. In this case, the polarities of the scan electrode 12A and the sustain electrode 12B can be inverted depending upon a voltage condition of the negative-going ramp voltage. Herein, if negative wall charges are left at the sustain electrode 12B, then they help a sustain discharge caused by the first sustain pulse in the sustain period SPD with the lapse of the address period APD. During such an application of the negative-going ramp pulse, a voltage of the data electrode 20 is fixed to a ground voltage 0V. Thus, the wall charges formed on the data electrode 20 by said positive-going ramp pulse cancels an external electric field, so that a discharge is not generated between the scan electrode 12A and the data electrode 20. Furthermore, since an amount of the wall charges formed on the scan electrode 12A by the secondary dark discharge is reduced, an address voltage applied to the scan electrode 12A or the data electrode 20 in the following address period SPD must be increased.
In the address period APD, a scan pulse SP having a voltage of Vsc is applied to the scan electrode 12A for each line and, at the same time, a data pulse DP having a voltage of Vd is applied to the data electrode 20 of the cell corresponding to a data ‘1’, thereby generating an address discharge. By this address discharge, the scan electrode 12A and the sustain electrode 12B are turned to an on state in which wall charges for the next sustain discharge are sufficiently formed. An amount of the wall charges formed by the address discharge is increased in accordance with an increase of the bias voltage BP applied to the sustain electrode 12B. Otherwise, since a voltage between the scan electrode 12A and the data electrode 20 fails to exceed a firing initiation voltage at the cells corresponding to a data ‘0’ and supplied with only the scan pulse SP, a discharge is not generated to keep an off state.
In the address period APD, when an address operation for each line has been finished, sustain pulses SUSPy and SUSPz are alternately to the scan electrode 12A and the sustain electrode 12B in the next sustain period SPD to keep a state of the cell determined in said address period. More specifically, the cells having an on state in which wall charges are sufficiently formed in the address period APD keep an on state owing to a discharge caused by the sustain pulses SUSPy and SUSPz, whereas the cells having an off state keep an off state as they are without any discharge.
In the erase period EPD following such a sustain period SPD, an erase pulse EP is applied to the sustain electrode 12B to cause an erasure discharge, thereby erasing wall charges existing in all the cells. In this case, a positive-going pulse is applied as the erase pulse EP so as to provide a small light-emission magnitude.
Such a selective write addressing method requires a write discharge interval of more than about 3 μs in order to sufficiently form wall charge required for the next sustain discharge with the aid of a write discharge according to a data pulse. Accordingly, there is raised a problem in that, since each of the scan pulse and the data pulse must have a pulse width of more than about 3 μs, the address period is lengthened and hence the sustain period becomes relatively insufficient, thereby causing a low brightness. Moreover, there occurs a problem in that, since the address period is more lengthened when it is intended to realize a high resolution picture, a gray level implementation becomes impossible due to a lack of the sustain period.
For instance, when red (R), green (G) and blue (B) discharge cells, 256 gray levels (8 bits) and a frame frequency of 60 Hz are considered for a high resolution of 1280×1024, a data amount to be processed is 1.75 Gbits (i.e., 1024×1280×3×8×60) per second, 30 Mbits (i.e., 1024×1280×3×8 bits) per frame (16.67 ms in the case of an image signal adopting the NTSC system) or 30 Kbits (i.e., 1280×3×8) per scan line. Furthermore, as a high resolution is heightened, a data amount to be processed is dramatically increased. Accordingly, since it is impossible for the selective write addressing method to display all the data with a high resolution with a limited time, there has been suggested a scheme of dividing a field into a plurality of blocks for a driving. However, a divisional driving of the field requires a greater number of driving circuits to drive each block to cause a cost rise.
In addition, the selective write addressing method requires a reset discharge for initializing all the cells by the entire write discharge so as to uniform a discharge condition such as internal electric fields of the discharge cells having kept an on state and the discharge cells having kept an off state at the previous sub-field. However, the reset discharge causes a spurious light generated every sub-field and failing to contribute to the brightness to thereby heighten a black level. Accordingly, a contrast ratio is reduced to deteriorate a display quality.
In order to solve such problems of the selective write addressing method having an insufficient sustain period, there has been suggested a selective erasure addressing method as shown in FIG. 6. The selective erasure addressing method generates a write discharge at all the cells to sufficiently form wall charges and then applies a scan pulse and a data pulse so as to selectively turn off a desired cell.
Referring to FIG. 6, at step S22, a write pulse is applied to all the cells of the panel to generate an entire write discharge, thereby allowing all the cells to be in an on state and forming wall charges sufficiently. At steps S24 to S28, the cells are selected in accordance with a display data to generate a wall charge erasure discharge at the cells to be turned to an off state with the aid of a scan pulse and a data pulse while sustaining sufficient wall charges formed at said step S22 without any discharge at the cells to be turned to an on state. At step S30, the sustain operation is performed to keep the on/off state of the cell determined at said steps S26 and S28 during the corresponding interval, thereby realizing a gray scale. Particularly, the cells in which the wall charges has been sufficiently kept without any discharge at said step S26 generates a sustain discharge during the corresponding interval. Subsequently, at step S32, an erasure operation allowing all the cells to have an off state is performed to prepare the next sub-field operation. At the next sub-field, the PDP repeats the operations of said steps S10 to S20.
Such a selective erasure addressing method requires a pulse width of about 1 μs so as to selectively turn off all the cells having an on state in the reset period by an erase discharge according to a data. Accordingly, the selective erasure addressing method permits a relatively high speed of driving in comparison to the selective write addressing method, so that it can improve the brightness owing to an increase of the sustain period and is suitable for realizing a high resolution picture. However, the selective erasure addressing method has a disadvantage in that the brightness at the off-state cell is too high in comparison to the selective write addressing method due to a light caused by the erase discharge. This reduces a contrast ratio to deteriorate a display quality. Moreover, the selective erasure addressing method requires a stable entire write discharge that allows all the cells to be in an on state at which wall charges are sufficiently formed in the reset period. To this end, since a stabilization discharge for equalizing the wall charges after the entire write discharge is added to the reset period, there is raised a problem in that a spurious light is increased to more deteriorate the contrast ratio.
As described above, the selective write addressing method and the selective erasure addressing method having been applied to the conventional PDP driving method have problems of a relatively long address period and a deterioration of contrast ratio. Therefore, there has been required a PDP driving method of improving a display quality while driving the PDP at a high speed.